Semiconductor memory module with bus architecture
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United States of America Patent
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Nov 20, 2007
Grant Date -
Aug 3, 2006
app pub date -
Feb 3, 2006
filing date -
Feb 3, 2005
priority date (Note) -
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Abstract
A semiconductor memory module, which is formed as an FBDIMM memory module, for example, has a planar design. In the 2R.times.4 configuration, semiconductor components are arranged in two rows on a top side of a module board and semiconductor memory components are likewise arranged in two rows on an underside of the module board. In contrast to a 'Stacked DRAM' design, the semiconductor components in accordance with the planar design contain only one memory chip. By using a parallel routing for a command address bus and an on-die termination bus, the address, clock, and control buses can be adapted in terms of load, so that different signal propagation times on the different buses are avoided to the greatest possible extent.
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