Hardware accelerated machine learning
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United States of America Patent
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Nov 9, 2021
Grant Date -
Jul 13, 2017
app pub date -
Jan 5, 2017
filing date -
Jan 7, 2016
priority date (Note) -
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Abstract
A machine learning hardware accelerator architecture and associated techniques are disclosed. The architecture features multiple memory banks of very wide SRAM that may be concurrently accessed by a large number of parallel operational units. Each operational unit supports an instruction set specific to machine learning, including optimizations for performing tensor operations and convolutions. Optimized addressing, an optimized shift reader and variations on a multicast network that permutes and copies data and associates with an operational unit that support those operations are also disclosed.
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