Voltage boosting circuit for a low power semiconductor memory
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United States of America Patent
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Apr 13, 2004
Grant Date -
N/A
app pub date -
Aug 30, 2002
filing date -
Aug 30, 2002
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An improved voltage boosting circuit operates entirely from a single, common VCC voltage supply. An NMOS pass transistor has a gate input terminal to which is connected a gate boost capacitor and a PMOS precharge circuit. A drain terminal of the NMOS pass transistor is connected to a drain boost capacitor and to a drain precharge circuit. The gate boost capacitor is precharged from the common VCC voltage. The second terminal of the precharged gate boost capacitor is connected to the common VCC voltage level to thereby boost the precharged gate input terminal voltage to 2 VCC. The drain of the NMOS pass transistor has a similar boost capacitor and precharge configuration. Another embodiment further includes an additional gate preboost capacitor and a gate preboost precharge circuit for boosting the gate voltage to 3 VCC to more efficiently drive the NMOS pass transistor.
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