Deposition pattern for eliminating backside metal peeling during die separation in semiconductor device fabrication
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United States of America Patent
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Apr 14, 2009
Grant Date -
Aug 30, 2007
app pub date -
Mar 27, 2007
filing date -
Nov 16, 2005
priority date (Note) -
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Abstract
A semiconductor wafer that includes a plurality of groups of active devices or circuits on a first side of the wafer and a patterned electrical contact on the backside of the wafer. Each group consisting of an active device or circuit is intended to be diced into a discrete chip. The backside of the wafer includes a metal layer patterned into discrete spaced-apart deposits that form an electrical contact to the semiconductor and the respective group of active devices. The deposits are not contiguously or laterally connected to each other and function to protect the metal layer from peeling or detaching from the wafer during dicing of the semiconductor wafer into chips.
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