Test method and test system for semiconductor device
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United States of America Patent
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Mar 14, 2006
Grant Date -
Dec 12, 2002
app pub date -
Dec 27, 2001
filing date -
Jun 8, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Method and system for shortening the time needed to test a semiconductor device having a plurality of memory circuits. The semiconductor device includes an address decoder for selecting a plurality of memory circuits and causing the memory circuits to perform a read/write operation. A comparator receives plural pieces of read data read from the plurality of memory circuits and compares the plural pieces of read data with one another. A processing unit compares one of the plural pieces of read data with write data. Using the comparison results of the comparator and the processing unit shorten the time needed to test the plurality of memory circuits.
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