Method for four direction low capacitance ESD protection
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United States of America Patent
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Mar 22, 2011
Grant Date -
Apr 23, 2009
app pub date -
Dec 23, 2008
filing date -
Jul 29, 2002
priority date (Note) -
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status (Latency Note)
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Abstract
The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Bss protection device. In addition, there is a heavily doped N+ guard ring surrounding the I/O protection device its P+ guard ring. The guard rings enhance structure diode elements providing enhanced ESD energy discharge path capability enabling the elimination of a specific conventional Vss to I/O pad ESD protection device. This reduces the capacitance seen by the I/O circuit while still providing adequate ESD protection for the active circuit devices.
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