Method for fabricating integrated circuits having both high voltage and low voltage devices
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United States of America Patent
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Aug 14, 2007
Grant Date -
Jan 26, 2006
app pub date -
Jul 25, 2004
filing date -
Jul 25, 2004
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Abstract
A high-voltage semiconductor MOS process that is fully compatible with low-voltage MOS process is provided. The high-voltage N/P well are implanted into the substrate prior to the definition of active areas. The channel stop doping regions are formed after the formation of field oxide layers, thus avoiding lateral diffusion of the channel stop doping regions. In addition, the grade drive-in process used to activate the grade doping regions in the high-voltage device area and the gate oxide growth of the high-voltage devices are performed simultaneously.
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