Base-to-substrate leakage cancellation
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United States of America Patent
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Aug 17, 2004
Grant Date -
N/A
app pub date -
Apr 14, 2003
filing date -
Apr 14, 2003
priority date (Note) -
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Abstract
The operating temperature range for a vertical PNP transistor can be extended by applying cancellation techniques. The vertical PNP generates a first leakage current from the base-collector region. Another vertical PNP transistor is configured to generate a second leakage current, which is coupled to a current-mirror circuit. The output of the current-mirror circuit is configured to provide a cancellation effect on the first leakage current. The current-mirror circuit and vertical PNP may be configured such that the first leakage current is cancelled in a judicious amount, whereby the effects of leakage current and flare-out in the vertical PNP transistor are minimized or cancelled. The cancellation technique is applicable to temperature sensor circuits, thermal voltage generators, and bandgap circuits.
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