Dual bus computer network using dual busses with dual spy modules enabling clearing of invalidation queue for processor with store through cache while providing retry cycles for incomplete accesses to invalidation queue
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United States of America Patent
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Apr 7, 1998
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N/A
app pub date -
Aug 21, 1996
filing date -
Apr 28, 1995
priority date (Note) -
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Abstract
A system and method for enhancing the rapidity of invalidation cycles in a processor having store-through cache holding 4-word data packets whereby an invalidation queue holds addresses of data to be invalidated in cache and the addresses are supplied by a system bus spy module which monitors the addresses of new data words selected for a write operation.
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