Multiple mode arithmetic circuit

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 11256476
APP PUB NO 20210042087A1
SERIAL NO

16535878

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Abstract

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A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.

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Patent Owner(s)

Patent OwnerAddress
ACHRONIX SEMICONDUCTOR CORPORATION2903 BUNKER HILL LANE SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fitton, Michael Philip Menlo Park, US 23 421
Nijssen, Raymond San Jose, US 20 107
Pugh, Daniel Los Gatos, US 12 34
Van, der Goot Marcel Pasadena, US 12 70

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