Semiconductor device
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United States of America Patent
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-
Nov 15, 2022
Grant Date -
Jul 8, 2021
app pub date -
Mar 19, 2021
filing date -
Sep 9, 2010
priority date (Note) -
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status (Latency Note)
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Abstract
A semiconductor device where delay or distortion of a signal output to a gate signal line in a selection period is reduced is provided. The semiconductor device includes a gate signal line, a first and second gate driver circuits which output a selection signal and a non-selection signal to the gate signal line, and pixels electrically connected to the gate signal line and supplied with the two signals. In a period during which the gate signal line is selected, both the first and second gate driver circuits output the selection signal to the gate signal line. In a period during which the gate signal line is not selected, one of the first and second gate driver circuits outputs the non-selection signal to the gate signal line, and the other gate driver circuit outputs neither the selection signal nor the non-selection signal to the gate signal line.
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