Pipeline analog-to-digital converter stages with improved transfer function
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United States of America Patent
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Aug 5, 2014
Grant Date -
Jul 25, 2013
app pub date -
Jan 23, 2013
filing date -
Jan 24, 2012
priority date (Note) -
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Abstract
A connection scheme is used to selectively connect a dither capacitor included in a calibrated stage of a pipeline analog-to-digital converter (ADC) in a way that reduces the output voltage swing of the stage. A first terminal of the dither capacitor is coupled to an input of the amplifier. A second terminal of the dither capacitor is coupled to either a first or second reference voltage dependent on a bit value in a Pseudo-Random Binary Sequence (PRBS) if a voltage received by the stage is within a first voltage range. If the stage received voltage is within a second range, the second terminal is coupled to the first reference voltage independent of the PRBS. If the stage received voltage is within a third range, the second terminal is coupled to the second reference voltage independent of the PRBS.
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