Contacts for semiconductor devices
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United States of America Patent
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Nov 28, 2023
Grant Date -
Sep 22, 2022
app pub date -
Mar 4, 2021
filing date -
Oct 20, 2006
priority date (Note) -
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status (Latency Note)
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Abstract
In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.
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