Method and apparatus to test the power-on-reset trip point of an integrated circuit
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United States of America Patent
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Apr 14, 2009
Issued Date -
N/A
app pub date -
Mar 31, 2006
filing date -
Mar 31, 2006
priority date (Note) -
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Abstract
Circuitry for testing a power-on-reset circuit in an integrated circuit includes a high-voltage detector coupled to a first I/O pad of the integrated circuit. A power-on-reset circuit in the integrated circuit has an output coupled to a driver circuit that is powered by the high-voltage. A second I/O pad of the integrated circuit is coupled to the output of the driver circuit. The driver circuit may be enabled by a signal provided on a third I/O pad of the integrated circuit.
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