Method for fabricating a split gate flash memory cell

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6713349
APP PUB NO 20040043563A1
SERIAL NO

10426347

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A method for fabricating a split gate flash memory cell. First, a substrate having a doped region covered by a first conductive layer is provided. A floating gate and a first insulating layer are successively formed over the substrate on both sides of the first conductive layer. Thereafter, a conformable second insulating layer and a conformable second conductive layer are successively formed on the substrate and the first insulating layer, and then a third insulating layer is formed thereon. The third insulating layer and the second conductive layer are successively etched back to expose the second insulating layer. The third insulating layer is removed using a cap layer formed on the second conductive layer as a mask to form an opening. Finally, the second conductive layer under the opening is removed to form a control gate underlying the cap layer.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

  • NANYA TECHNOLOGY CORPORATION

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Huang, Chung-Lin Taichung, TW 102 304
Lin, Chi-Hui Taipei, TW 46 319

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation