Memory controller and memory control method that decides an order of issuing dram commands based on whether a command has a penalty period
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United States of America Patent
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Dec 12, 2023
Grant Date -
Jul 21, 2022
app pub date -
Apr 4, 2022
filing date -
Aug 30, 2019
priority date (Note) -
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status (Latency Note)
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Abstract
A memory controller that is formed to be able to issue a first write command for writing data of a predetermined length into a DRAM and a second write command for writing data which is less than the predetermined length in the DRAM is provided. The memory controller comprises a deciding unit configured to decide an issuance order of a request stored in the storage unit. In a period from the issuance of a preceding DRAM command until a second write command targeting the same bank as the preceding DRAM command is issued, if another DRAM command targeting a bank different from the bank targeted by the preceding DRAM command can be issued, the deciding unit will decide the issuance order so that the other DRAM command that can be issued will be issued before the second write command.
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