High strength low stress encapsulation of interconnected semiconductor devices
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United States of America Patent
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Sep 10, 1991
Issued Date -
N/A
app pub date -
Aug 27, 1990
filing date -
Jun 20, 1989
priority date (Note) -
Expired
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Abstract
A semiconductor packaging technique employing a high Young's modulus, localized, external connection to pad, bond immobilizing member, together with, as needed, a low Young's modulus environmental protection covering member. A chip of Si or GaAs has an annulus of high Young's modulus epoxy over the line of external connections such as beam leads or wire bonds near the edge and a coating of silicone over the entire chip surface including the annulus.
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