Address-based hazard resolution for managing read/write operations in a memory cache
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United States of America Patent
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Jan 28, 2014
Grant Date -
Aug 2, 2012
app pub date -
Jan 31, 2011
filing date -
Jan 31, 2011
priority date (Note) -
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Abstract
One embodiment provides a cached memory system including a memory cache and a plurality of read-claim (RC) machines configured for performing read and write operations dispatched from a processor. According to control logic provided with the cached memory system, a hazard is detected between first and second read or write operations being handled by first and second RC machines. The second RC machine is suspended and a subset of the address bits of the second operation at specific bit positions are recorded. The subset of address bits of the first operation at the specific bit positions are broadcast in response to the first operation being completed. The second operation is then re-requested.
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