Importance

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Abstract

A programmable logic device (PLD) implementing an SDRAM controller is provided. The configurable logic of the PLD forms an interface between the system and the SDRAM, as well as a state machine to operate the controller and the interface. In this manner, many functions of the SDRAM controller can be selectively controlled and easily changed by reprogramming the PLD. The configurable logic of the PLD also forms a state machine to operate the controller and the interface. In accordance with the present invention, dedicated circuits of the PLD optimize performance of the SDRAM controller. These dedicated circuits include two delay locked loops (DLLs) which eliminate skew between the system clock, a global clock in the PLD, and the SDRAM clock.

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First Claim