EEPROM memory cell array architecture for substantially eliminating leakage current
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United States of America Patent
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Mar 23, 2004
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N/A
app pub date -
Oct 3, 2002
filing date -
Oct 3, 2002
priority date (Note) -
Expired
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Abstract
An EEPROM memory cell array architecture (50) that substantially eliminates leakage current to allow for reading memory cells (20) in a memory cell array of, for example, a CPLD at lower voltages than are possible with prior art architectures, thereby facilitating development of low voltage applications. This is accomplished by associating each wordline of the memory cell array with a ground transistor (26). On one embodiment, the ground transistor (26) can be a high voltage transistor, in which case the same high voltage control signal can control both the ground transistor (26) and the memory cell=s read transistor (32). In another embodiment, the ground transistor (26) is a low voltage transistor controlled by a separate low voltage control signal.
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