Methods of forming contact structures for memory cells using both anisotropic and isotropic etching
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United States of America Patent
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Jun 8, 2010
Grant Date -
Jun 30, 2005
app pub date -
Jul 26, 2004
filing date -
Dec 30, 2003
priority date (Note) -
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Abstract
Methods of forming a cell of a NOR-type flash memory device are provided in which a first gate pattern having a first sidewall and a second gate pattern having a second sidewall that opposes the first sidewall are formed on a semiconductor substrate. A source/drain region is formed in the semiconductor substrate between the first and second gate patterns. An etch stop layer is formed on the first and second sidewalls that defines a gap region. A dielectric layer is formed in the gap region, and is then etched to form a contact hole. Finally, a conductive material is deposited in the contact hole.
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