Selectable address translation mechanisms within a partition
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United States of America Patent
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Aug 22, 2017
Issued Date -
N/A
app pub date -
Mar 7, 2013
filing date -
Oct 8, 2012
priority date (Note) -
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status (Latency Note)
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Abstract
An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration. For a system configuration that includes partitions, the translation mechanism to be used for a partition or a portion thereof is selectable and may be different for different partitions or even portions within a partition.
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