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Abstract

Methods which provide for the formation of the intrinsic base regions and the link-up regions in separate processing steps are provided. These methods include the steps of forming a first conductive layer on a substrate of a first conductivity type containing a region of a second conductivity type therein, wherein the first conductive layer is formed on the region of second conductivity type semiconductor material. The first conductive layer is patterned to define a sidewall of a window which exposes a portion of the region of a second conductivity type semiconductor material. An insulating layer is formed on the sidewall, the first conductive layer and the exposed portion of the region of second conductivity type semiconductor material. A first mask is then formed on the insulating layer which exposes a region of the insulating layer corresponding to a link-up region of the bipolar transistor. A first impurity ion of a first conductivity type is then implanted through the insulating layer using the first mask to form a link-up region. The first mask may be removed and a sidewall spacer formed on the sidewall. The insulating layer is then removed to expose a region of second conductivity type semiconductor material adjacent the sidewall spacer to define an implantation region for an intrinsic base region. A second impurity ion of the first conductivity type is then implanted in the region of second conductivity type semiconductor material using the sidewall spacer as a mask to form an intrinsic base region. Thus, an intrinsic base region and a link-up region are formed separately.

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First Claim