Semiconductor devices including a topmost metal layer with at least one opening and their methods of fabrication
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Aug 6, 2013
Grant Date -
Dec 2, 2010
app pub date -
Aug 13, 2010
filing date -
Jun 17, 2005
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
In one embodiment, a semiconductor device has a topmost or highest conductive layer with at least one opening. The semiconductor device includes a semiconductor substrate having a cell array region and an interlayer insulating layer covering the substrate having the cell array region. The topmost conductive layer is disposed on the interlayer insulating layer in the cell array region. The topmost conductive layer has at least one opening. A method of fabricating the semiconductor device is also provided. The openings penetrating the topmost metal layer help hydrogen atoms reach the interfaces of gate insulating layers of cell MOS transistors and/or peripheral MOS transistors during a metal alloy process, thereby improve a performance (production yield and/or refresh characteristics) of a memory device.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully