Peripheral interface circuit for serial memory
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United States of America Patent
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Jul 28, 2020
Grant Date -
Jan 24, 2019
app pub date -
Sep 24, 2018
filing date -
Apr 2, 2015
priority date (Note) -
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Abstract
A peripheral interface circuit and method is disclosed for dealing with round trip delay with serial memory. In some implementations, a finite state machine is configured to introduce a delay state prior to a read data state to absorb round trip delay associated with a memory read operation. A clock module is coupled to the finite state machine and configured to delay start of a pad return clock for the read operation until completion of the delay state. A first synchronous logic is coupled to receive the pad return clock and is configured to sample and hold data from a data bus during the read data state of the memory read operation based on the pad return clock. A second synchronous logic is coupled to receive a system clock and is configured to sample the held data based on the system clock.
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