Memory circuit and semiconductor device
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Aug 26, 2014
Grant Date -
Aug 22, 2013
app pub date -
Jan 29, 2013
filing date -
Feb 17, 2012
priority date (Note) -
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status (Latency Note)
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Abstract
Included is a first transistor for controlling rewriting and reading of a first data, a second transistor for controlling rewriting and reading of a second data, a first inverter including an input terminal for the first data, a second inverter including an input terminal for the second data, a third transistor between an output terminal of the second inverter and the input terminal of the first inverter, a fourth transistors between the output of the first inverter and the input terminal of the second inverter, a fifth transistor for controlling rewriting and reading of the first data in the first capacitor, and a sixth transistor for controlling rewriting and reading of the second data in a second capacitor. The first data and the second data are held in the first capacitor and the second capacitor even while power supply is cut off.
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