Hardware accelerator method, system and device

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United States of America Patent

PATENT NO 11442700
APP PUB NO 20200310761A1
SERIAL NO

16833340

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Abstract

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A system includes an addressable memory array, one or more processing cores, and an accelerator framework coupled to the addressable memory. The accelerator framework includes a Multiply ACcumulate (MAC) hardware accelerator cluster. The MAC hardware accelerator cluster has a binary-to-residual converter, which, in operation, converts binary inputs to a residual number system. Converting a binary input to the residual number system includes a reduction modulo 2m and a reduction modulo 2m−1, where m is a positive integer. A plurality of MAC hardware accelerators perform modulo 2m multiply-and-accumulate operations and modulo 2m−1 multiply-and-accumulate operations using the converted binary input. A residual-to-binary converter generates a binary output based on the output of the MAC hardware accelerators.

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Patent Owner(s)

  • SMI STMICROELECTRONICS S.R.L; STMICROELECTRONICS INTERNATIONAL N.V.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Boesch, Thomas Rovio, CH 35 434
Cappetta, Carmine Battipaglia, IT 7 20
Desoli, Giuseppe San Fermo Della Battaglia, IT 53 1078
Rossi, Michele Salerno, IT 13 106

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