Forward progress mechanism for stores in the presence of load contention in a system favoring loads
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United States of America Patent
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Aug 5, 2014
Grant Date -
Aug 8, 2013
app pub date -
Nov 16, 2012
filing date -
Feb 8, 2012
priority date (Note) -
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Abstract
A multiprocessor data processing system includes a plurality of cache memories including a cache memory. In response to the cache memory detecting a storage-modifying operation specifying a same target address as that of a first read-type operation being processed by the cache memory, the cache memory provides a retry response to the storage-modifying operation. In response to completion of the read-type operation, the cache memory enters a referee mode. While in the referee mode, the cache memory temporarily dynamically increases priority of any storage-modifying operation targeting the target address in relation to any second read-type operation targeting the target address.
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