Wafer scale testing using a 2 signal JTAG interface
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United States of America Patent
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Aug 4, 2009
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N/A
app pub date -
Jul 18, 2008
filing date -
Dec 2, 2005
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Abstract
Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.
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