Damascene pattering of SOI MOS transistors
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United States of America Patent
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Apr 6, 1999
Grant Date -
N/A
app pub date -
Oct 22, 1997
filing date -
Oct 22, 1997
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The present invention is a technique for producing planar silicon on insulator MOS transistors, where the channel regions are created in an underlying single crystal silicon wafer, and where the source-drain extension regions are created by damascene patterning a thin film of amorphous silicon deposited on a layer of oxide deposited on the silicon wafer.
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