Process of fabricating an anti-fuse for avoiding a key hole exposed
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United States of America Patent
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Sep 9, 2003
Grant Date -
May 15, 2003
app pub date -
Nov 30, 2001
filing date -
Nov 12, 2001
priority date (Note) -
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status (Latency Note)
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Abstract
A process of forming an anti-fuse. First, an inter-metal dielectric layer, in which a funnel-shaped via is formed, is formed on a substrate. Next, a first conductive layer is formed over the substrate and filled into the funnel-shaped via. Subsequently, by, for example, a chemical mechanical polishing process, the first conductive layer outside the funnel-shaped via is removed to form a conductive plug. Afterward, an oxide chemical mechanical polishing process is performed to smooth the surface of the conductive plug. Next, a dielectric layer is formed on the top side of the conductive plug, and then a top plate is formed on the dielectric layer. Subsequently, an insulating layer is formed over the substrate, wherein the insulating layer is provided with a via and the via exposes the top plate. Finally, a second conductive layer is formed over the substrate and filled into the via.
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