Latched address multi-chunk write to EEPROM
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United States of America Patent
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Feb 15, 2011
Grant Date -
Sep 10, 2009
app pub date -
May 20, 2009
filing date -
Nov 5, 1996
priority date (Note) -
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Abstract
An EEPROM system includes flash EEPROM cells organized into subarrays. Pairs of subarrays share row address decoders by sharing word lines, and individual subarrays have dedicated column address decoders and data registers. Each row decoder has an associated row address latch, and each column decoder has an associated column address latch. Multiple data chunks are concurrently written into the subarrays by first latching chunk addresses into the row and column address latches, and corresponding chunks of data into the data registers, then activating a programming signal to initiate concurrent programming and verifying the programming of the data chunks.
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