Deck-level signal development cascodes
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United States of America Patent
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Dec 5, 2023
Grant Date -
Mar 2, 2023
app pub date -
Aug 31, 2021
filing date -
Aug 31, 2021
priority date (Note) -
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status (Latency Note)
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Abstract
Methods, systems, and devices for deck-level signal development cascodes are described. A memory device may include transistors that support both a signal development and decoding functionality. In a first operating condition (e.g., an open-circuit condition), a transistor may be operable to isolate first and second portions of an access line based on a first voltage applied to a gate of the transistor. In a second operating condition (e.g., a signal development condition), the transistor may be operable to couple the first and second portions of the access line and generate an access signal based on a second voltage applied to the gate of the transistor. In a third operating condition (e.g., a closed-circuit condition), the transistor may be operable to couple the first and second portions of the access line based on applying a third voltage greater than the second voltage to the gate of the transistor.
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