Computer system with redundancy having fail test mode

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United States of America Patent

PATENT NO 11810634
APP PUB NO 20220351797A1
SERIAL NO

17243086

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Disclosed herein is an apparatus that includes a data terminal, a memory cell array, a mode register storing a plurality of operation parameters, and an output circuit configured to output, in response to a read command, an incorrect data to the data terminal instead of a correct data read from the memory cell array when a predetermined one of the operation parameters indicates a test mode.

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Patent Owner(s)

  • MICRON TECHNOLOGY INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Okuma, Sadayuki Tama, JP 16 111

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