Memory cell and method of forming the memory cell
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United States of America Patent
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Dec 12, 2023
Grant Date -
Oct 7, 2021
app pub date -
Apr 7, 2020
filing date -
Apr 7, 2020
priority date (Note) -
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Abstract
A memory cell includes: a first transistor, having a first diffusion region coupled to a bit line and a first gate electrode coupled to a first word line; a second transistor, having a second diffusion region coupled to the bit line and a second gate electrode coupled to a second word line; and a third transistor, having a third diffusion region coupled to a fourth diffusion region of the first transistor, a fifth diffusion region coupled to a sixth diffusion region of the second transistor, and a third gate electrode coupled to a third word line; wherein the first transistor is arranged to have a first threshold voltage, the second transistor is arranged to have a second threshold voltage, and the second threshold voltage is different from the first threshold voltage.
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