Importance

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Abstract

A memory array of a static RAM or the like is divided in a word line extending direction to constitute a plurality of sub memory arrays SM0 to SM7, and array selecting signals for selecting the sub memory arrays and sub word line selecting signals for selecting sub word lines are combined to form word line selecting signals selectively. Main word lines M0000 to M0003 for transmitting those word line signals are arranged in parallel with the sub word lines SW000 to SW255. Sub word line drive circuits SWD000 to SWD255 are also coupled to the individual sub word lines for bringing the corresponding sub word lines selectively into selected states by combining at least 2 bits of the word line selecting signals.

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First Claim