Method of manufacturing an etch stop layer and an inter-layer dielectric on a source/drain region
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United States of America Patent
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Dec 6, 2022
Grant Date -
N/A
app pub date -
Jan 11, 2021
filing date -
Aug 14, 2020
priority date (Note) -
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status (Latency Note)
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Abstract
In an embodiment, a device includes: a gate structure over a substrate; a gate spacer adjacent the gate structure; a source/drain region adjacent the gate spacer; a first inter-layer dielectric (ILD) on the source/drain region, the first ILD having a first concentration of an impurity; and a second ILD on the first ILD, the second ILD having a second concentration of the impurity, the second concentration being less than the first concentration, top surfaces of the second ILD, the gate spacer, and the gate structure being coplanar; and a source/drain contact extending through the second ILD and the first ILD, the source/drain contact coupled to the source/drain region.
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