Importance

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Abstract

A nonvolatile memory device includes a memory cell region having a first metal pad and a peripheral circuit region having a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a a memory cell array in the memory cell region and an address decoder in the peripheral circuit region. The memory cell array includes memory blocks, and each memory block includes memory cells coupled to word-lines respectively. The word-lines are stacked vertically on a substrate, and some memory cells of the plurality of memory cells are selectable by a sub-block unit smaller than one memory block of the plurality of memory blocks. The address decoder applies an erase voltage to each of sub-blocks in a first memory block of the plurality of memory blocks through the first metal pad and the second metal pad.

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First Claim