Control logic implementation for a non-blocking switch network
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United States of America Patent
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Mar 27, 2007
Grant Date -
Oct 17, 2002
app pub date -
Mar 8, 2002
filing date -
Mar 9, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The present invention relates to switching technology in computer networks and in particular to a method and system for switching information packets through a m input, n output device. According to the invention it is proposed to temporarily buffer said packets according to a new, self-explanatory, preferred a linear addressing scheme in which a respective buffer location of consecutive stream packets results from a respective self-explanatory, or linear, respectively, incrementation of a buffer pointer. Preferably, a matrix of FIFO storage elements (10,11,12,13) having an input and an output crossbar can be used for implementing input/output paralleling modes (ILP,OLP) and multiple lanes and achieving address input/output scaling up to a single cycle.
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