Method of manufacturing buried metal lines having ultra fine features

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United States of America Patent

PATENT NO 6429123
SERIAL NO

09679270

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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The present invention provides a method for manufacturing a plurality of buried metal lines on a semiconductor substrate. The method comprises the steps as below. A dielectric layer is formed on a semiconductor substrate. And a plurality of insulator blocks are formed on the dielectric layer, wherein each the insulator block has a width of 3 unit (3.times.), and each gap between two adjacent the insulator blocks has a width of 5 unit (5.times.). First sidewall spacers are formed on sidewalls of the insulator blocks, wherein each the first sidewall spacer has a width of 1 unit (1.times.). Then the plurality of the insulator blocks are removed, and second sidewall spacers are defined on sidewalls of the first sidewall spacers, wherein each the second sidewall spacer has a width of 1 unit (1.times.). Next studs are formed into gaps between two adjacent the second sidewall spacers, wherein each the stud has a width of 1 unit (1.times.). And the second sidewall spacers are removed. Then the dielectric layer is etched anisotropically to form a plurality of trenches in the dielectric layer by using said first sidewall spacers and the studs to serve as etching masks. A metal layer is deposited to fill into the trenches to form a plurality of metal lines.

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Patent Owner(s)

  • VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Tseng, Horng-Huei Hsinchu, TW 445 4702

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