Semiconductor memory device
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United States of America Patent
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Aug 19, 2008
Grant Date -
May 3, 2007
app pub date -
Oct 27, 2006
filing date -
Nov 1, 2005
priority date (Note) -
In Force
status (Latency Note)
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Abstract
Disclosed is a semiconductor memory device comprising a memory cell array block, and a circuit region arranged with the memory cell array block along a first direction. The circuit region comprises a first region and a second region arranged with the first region along the first direction. The first region is provided with a first circuit and a second circuit which are aligned in a second direction perpendicular to the first direction. The second region is provided with a plurality of third circuits which are aligned in the second direction.
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