Semiconductor memory device delaying ATD pulse signal to generate word line activation signal
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Oct 26, 1999
Grant Date -
N/A
app pub date -
Mar 12, 1999
filing date -
Aug 28, 1998
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A word line activation signal generated by a timing generator is surely at L level in a prescribed period regardless of the power supply voltage. A row address signal delayed by a delay circuit in a row address buffer changes in a period in which the word line activation signal is at L level. Accordingly, even if skew occurs, a non-selected word line is never activated. Consequently, it is possible to prevent delay of access to a memory cell and erroneous writing to a memory cell.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully