Sense amplifier activation timing scheme to suppress disturbance in memory cells of dram memory device

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 11735250
APP PUB NO 20220246198A1
SERIAL NO

17395964

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A semiconductor memory device is provided to suppress occurrence of disturbance regardless of the position of the activated word line. The semiconductor memory device includes a plurality of word lines, a bit line, a plurality of memory cells connected to the bit line and one of the plurality of word lines, a sense amplifier connected to the bit line, and a control portion. The control portion is configured to control timing of activating the sense amplifier. When a position of an activated word line among the plurality of word lines is closer to the sense amplifier, the control portion controls the timing of activating the sense amplifier to be delayed more.

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Patent Owner(s)

  • WINBOND ELECTRONICS CORP.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Sato, Takahiko Yokohama, JP 68 434

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