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Abstract

A processing pipeline is disclosed for use with a computer having a vector register. The processing pipeline processes a logical expression including binary operand elements and operator elements successively supplied from the vector register, and stores resulting data into the vector register. The processing pipeline includes a first pushdown stack, coupled to the vector register to receive binary operand elements of the logical expression; a second pushdown stack, coupled to said vector register to receive operator elements of the logical expression; a character register to temporarily store an operator element of the logical expression during processing; and a processor for processing the logical expression, including an error detector for detecting errors in the logical expression based on a relationship between a first operator element in the character register and a second operator element at a top of the second pushdown stack.

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First Claim