Method of forming different oxide thickness for high voltage transistor and memory cell tunnel dielectric
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United States of America Patent
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Aug 1, 2006
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N/A
app pub date -
May 19, 2004
filing date -
Dec 5, 2001
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Abstract
A semiconductor memory device and method for making the same, where a memory cell and high voltage MOS transistor are formed on the same substrate. An insulating layer is formed having a first portion that insulates the control and floating gates of the memory cell from each other, and a second portion that insulates the poly gate from the substrate in the MOS transistor. The insulating layer is formed so that its first portion has a smaller thickness than that of its second portion.
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