Method of fabricating a high performance MOSFET device featuring formation of an elevated source/drain region

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United States of America Patent

PATENT NO 7129547
SERIAL NO

10971624

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Abstract

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A method of fabricating a MOSFET device featuring a raised source/drain structure on a heavily doped source/drain region as well as on a portion of a lightly doped source/drain (LDD), region, after removal of an insulator spacer component, has been developed. After formation of an LDD region a composite insulator spacer, comprised of an underlying silicon oxide spacer component and an overlying silicon nitride spacer component, is formed on the sides of a gate structure. Formation of a heavily doped source/drain is followed by removal of the silicon nitride spacer resulting in recessing of, and damage formation to, the heavily doped source/drain region, as well as recessing of the gate structure. Removal of a horizontal component of the silicon oxide spacer component results in additional recessing of the heavily doped source/drain region, and of the gate structure. A selective epitaxial growth procedure is then used to form a raised, single crystalline silicon structure on the recessed and damaged heavily doped source/drain and LDD regions, while a polycrystalline silicon structure is grown on the underlying recessed gate structure. Metal silicide is then formed on the raised, single crystalline silicon structure and on the polycrystalline silicon structure.

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Patent Owner(s)

  • TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chang, Chih-Sheng Hsin-Chu, TW 202 4183
Wang, Yin-Pin Kaohsiung, TW 20 281

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