Simplified vertical array device DRAM/eDRAM integration: method and structure
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United States of America Patent
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Feb 3, 2009
Grant Date -
Oct 12, 2006
app pub date -
Apr 8, 2005
filing date -
Apr 8, 2005
priority date (Note) -
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Abstract
The present invention provides a semiconductor structure that includes an active wordline located above a semiconductor memory device and a passive wordline located adjacent to said active wordline and above an active area of a substrate. In accordance with the present invention, the passive wordline is separated from the active area by a pad nitride. The present invention also provides methods that are capable of forming the inventive semiconductor structure.
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