Synchronization amongst processor tiles

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United States of America Patent

PATENT NO 11586483
SERIAL NO

17320904

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Abstract

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A processing system comprising an arrangement of tiles and an interconnect between the tiles. The interconnect comprises synchronization logic for coordinating a barrier synchronization to be performed between a group of the tiles. The instruction set comprises a synchronization instruction taking an operand which selects one of a plurality of available modes each specifying a different membership of the group. Execution of the synchronization instruction cause a synchronization request to be transmitted from the respective tile to the synchronization logic, and instruction issue to be suspended on the respective tile pending a synchronization acknowledgement being received back from the synchronization logic. In response to receiving the synchronization request from all the tiles in the group as specified by the operand of the synchronization instruction, the synchronization logic returns the synchronization acknowledgment to the tiles in the specified group.

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Patent Owner(s)

  • GRAPHCORE LIMITED

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Alexander, Alan Graham Wotton-Under-Edge, GB 32 145
Felix, Stephen Bristol, GB 96 432
Fyles, Matthew David Wiltshire, GB 13 131
Knowles, Simon Christian Corston, GB 30 121
Wilkinson, Daniel John Pelham West Harptreee, GB 54 246

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