Method and circuit for scan dump of latch array

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United States of America Patent

PATENT NO 11443823
SERIAL NO

17468066

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Abstract

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Testability of memory on integrated circuits is improved by connecting storage elements like latches in memory to scan chains and configuring memory for scan dump. The use of latches and similar compact storage elements to form scannable memory can extend the testability of high-density memory circuits on complex integrated circuits operable at high clock speeds. A scannable memory architecture includes an input buffer with active low buffer latches, and an array of active high storage latches, operated in coordination to enable incorporation of the memory into scan chains for ATPG/TT and scan dump testing modes.

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Patent Owner(s)

  • SAMBANOVA SYSTEMS, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Amirtharaj, Dinesh R Milpitas, US 3 1
Durairajan, Uma San Jose, US 9 20
Ziaja, Thomas A Austin, US 7 89

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