Processing in memory (PIM)capable memory device having timing circuity to control timing of operations
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United States of America Patent
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Feb 28, 2023
Grant Date -
May 13, 2021
app pub date -
Jan 25, 2021
filing date -
Mar 10, 2016
priority date (Note) -
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Abstract
Apparatuses and methods are provided for logic/memory devices. An example apparatus comprises a plurality of memory components adjacent to and coupled to one another. A logic component is coupled to the plurality of memory components. At least one memory component comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component. Timing circuitry is coupled to the array and sensing circuitry and configured to control timing of operations for the sensing circuitry. The logic component comprises control logic coupled to the timing circuitry. The control logic is configured to execute instructions to cause the sensing circuitry to perform the operations.
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